# US 11,552,104 B2 · Stacked transistors with dielectric between channels of different device strata

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- Number: US 11,552,104 B2
- Document ID: US11552104B2
- Status: Granted
- Kind: B2
- Application number: 16/279,693
- Filed: 2019-02-19
- Published: 2020-08-20
- Granted: 2023-01-10
- Earliest claimed: 2019-02-19
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Aaron D. Lilak; Gilbert W. Dewey; Willy Rachmady; Rishabh Mehandru; Ehren Mannebach; Cheng-Ying Huang; Anh Phan; Patrick Morrow; Kimin Jun
- Web page: https://patentgrep.com/patent/US11552104B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 86/215: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 86/011: {comprising FinFETs}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric.

## Claims

### Claim 1

An integrated circuit (IC) structure, comprising:
a first device stratum including a first channel material and a first gate metal;
a second device stratum including a second channel material and a second gate metal, wherein the second channel material is above and aligned with the first channel material; and
a dielectric material between the first channel material and the second channel material, wherein the dielectric material is surrounded by a gate metal along a cross-section perpendicular to a longitudinal axis of the first channel material, and the gate metal includes the first gate metal or the second gate metal.

### Claim 2 (depends on 1)

The IC structure of claim 1, wherein the first device stratum includes a first gate dielectric, the second device stratum includes a second gate dielectric, and the dielectric material is at least partially surrounded by a gate dielectric, and the gate metal includes the first gate dielectric or the second gate dielectric.

### Claim 3 (depends on 2)

The IC structure of claim 2, wherein the dielectric material is surrounded by the gate dielectric along the cross-section perpendicular to the longitudinal axis of the first channel material.

### Claim 4 (depends on 1)

The IC structure of claim 1, wherein the first channel material or the second channel material includes a semiconductor fin and the semiconductor fin is in contact with the dielectric material.

### Claim 5 (depends on 4)

The IC structure of claim 4, wherein the first channel material or the second channel material includes a plurality of semiconductor wires.

### Claim 6 (depends on 1)

The IC structure of claim 1, wherein the dielectric material includes nitrogen, carbon, or oxygen.

### Claim 7 (depends on 1)

The IC structure of claim 1, wherein the dielectric material includes carbon and nitrogen.

### Claim 8 (depends on 1)

The IC structure of claim 1, wherein the dielectric material is an interlayer dielectric.

### Claim 9 (depends on 1)

The IC structure of claim 1, wherein a height of the dielectric material is between 20 nanometers and 200 nanometers.

### Claim 10 (depends on 1)

The IC structure of claim 1, wherein the first device stratum is between a silicon-on-insulator structure and the second device stratum.

### Claim 11

An integrated circuit (IC) die, comprising:
a first device stratum including a first channel material, wherein the first channel material includes a plurality of semiconductor wires;
a second device stratum including a second channel material, wherein the second channel material includes a plurality of semiconductor wires; and
a dielectric material between the first channel material and the second channel material, wherein the dielectric material is surrounded by a gate metal along a cross-section perpendicular to a longitudinal axis of a semiconductor wire of the first channel material.

### Claim 12 (depends on 11)

The IC die of claim 11, wherein the plurality of semiconductor wires of the first channel material are coplanar with the plurality of semiconductor wires of the second channel material.

### Claim 13 (depends on 11)

The IC die of claim 11, wherein the semiconductor wires of the first and second channel materials are surrounded by the gate metal.

### Claim 14 (depends on 11)

The IC die of claim 11, wherein the first device stratum includes first source/drain materials at opposing ends of the first channel material, and the second device stratum includes a second source/drain materials at opposing ends of the first channel material, and at least one of the first source/drain materials is in contact with at least one of the second source/drain materials.

### Claim 15 (depends on 11)

The IC die of claim 11, wherein a spacer material is between the dielectric material and first source/drain materials and between the dielectric material and second source/drain materials.

### Claim 16 (depends on 11)

The IC die of claim 11, further comprising:
a plurality of conductive contacts at an outer face of the IC die, wherein at least some of the conductive contacts are in electrical contact with the first device stratum or the second device stratum.

### Claim 17

A computing device, comprising:
a circuit board; and
an integrated circuit (IC) package coupled to the circuit board, wherein the IC package includes a package substrate and an IC die coupled to the package substrate, and the IC die includes stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate metal along a cross-section perpendicular to a longitudinal axis of the channel materials.

### Claim 18 (depends on 17)

The computing device of claim 17, wherein the circuit board is a motherboard.

### Claim 19 (depends on 17)

The computing device of claim 17, wherein the computing device is a tablet computing device, a handheld computing device, a smart phone, a wearable computing device, or a server.