JTAG bus communication method and apparatus
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
Claims17
An integrated circuit comprising;
- (a) an interface having a test data input adapted to receive data input signals, a test data output adapted to send data output signals, a test clock input adapted to receive clock signals having rising and falling edges, and a test mode select terminal adapted to receive test mode select signals;
- (b) a test port coupled to the interface, the test port including:
- (i) a state machine having inputs coupled to the test clock input and the test mode select terminal and having control outputs providing control signals, the state machine staying in states and stepping between states in response to the test mode select signals on falling edges of the clock signals;
- (ii) a data register having a register input coupled to the test data input, having a register output coupled to the test data output, having a control input coupled to a control output, and having an input coupled to the test clock input, the data register shifting data from the register input to the register output in response to a control signal and the clock signals;
- (iii) an instruction register having an instruction input coupled to the test data input, having an instruction output coupled to the test data output, having a control input coupled to a control output, and having an input coupled to the test clock input, the instruction register shifting data from the instruction input to the instruction output in response to a control signal and the clock signals;
- (c) communication circuitry coupled to the test mode select terminal, the communication circuitry adapted to communicate data signals over the test mode select terminal while the test clock signals are free of falling edges.
Dependencies are inferred from the claim text.