Traversing a variable delay line in a deterministic number of clock cycles

A system comprising:

• an input clock rotating register configured to be initialized by a reset signal, wherein the reset signal received by the input clock rotating register is synchronized to an input clock signal;
• an output clock rotating register configured to be initialized by the reset signal, wherein the reset signal received by the output clock rotating register is synchronized to an output clock signal, the output clock signal initialized via a variable delay line, the variable delay line configured to delay the input clock signal based on a number of offset cycles provided to the variable delay line;
• a plurality of mux-flops configured to receive a data input synchronized to the output clock signal, wherein the output clock signal rotating register activates one of the plurality of mux-flops to receive the data input;
• and
• a multiplexer configured to receive the data input, via the plurality of mux-flops, the multiplexer receiving a selection input of the input clock rotating register, wherein the multiplexer selects the data input as the output of the multiplexer using the selection input to be a data output signal, such that the data output is synchronized with the input clock.

A non-transitory computer readable medium storing instructions thereon, the instructions, when executed by a processor, cause the processor to:

• initialize an input clock rotating register by sending a reset signal, wherein the reset signal received by the input clock rotating register is synchronized to an input clock signal;
• initialize an output clock signal via a variable delay line, the variable delay line configured to delay the input clock signal based on a number of offset cycles provided to the variable delay line;
• initialize an output clock rotating register by sending the reset signal, wherein the reset signal received by the output clock rotating register is synchronized to an output clock signal;
• provide a data input synchronized to the output clock signal to a plurality of mux-flops, wherein the output clock rotating register activates one of the plurality of mux-flops to receive the data input;
• forward the data input via the one of the plurality of mux-flops to a multiplexer, wherein the multiplexer is coupled to receive the outputs of the plurality of mux-flops as data inputs and wherein the input clock rotating register controls the data input selected by the multiplexer as its output;
• and
• select the data input as the output of the multiplexer to be a data output signal, such that the data output is synchronized with the input clock.