CMOS image sensors with integrated RRAM-based crossbar array circuits

An apparatus comprising:

• a complementary metal-oxide semiconductor (CMOS) image sensor having one or more pixels configured to receive image signals;
• a column decoder configured to select the pixels in columns to read out;
• a row decoder configured to select the pixels in rows to read out;
• an amplifier configured to amplify first signals received from the CMOS image sensor;
• a multiplexer configured to sequentially or serially read out second signals received from the amplifier;
• and
• an IMC (in-memory-computing) crossbar array circuit having one or more IMC cells configured to store and process third signals received from the multiplexer, wherein the one or more IMC cells include a Metal-Insulator-Metal (MIM) structure and a transistor serially connected to the MIM structure, and wherein the third signals are read out by the IMC crossbar array circuit from the multiplexer in parallel, and wherein the third signals correspond to pixel data generated by the CMOS image sensor.