Enhanced discrete-time feedforward equalizer

An apparatus, comprising:

• a set of N sample-and-hold (S/H) circuits coupled together in series;
• a filter coupled between the (N−1)th S/H circuit and the Nth S/H circuit;
• a set of N transconductance stages, wherein each transconductance stage is coupled to an output of a unique S/H circuit in the N S/H circuits;
• and
• a summer coupled to outputs of the N transconductance stages.

A feedforward equalizer (FFE), comprising:

• a first sample and hold (S/H) circuit configured to receive an input signal and a clock signal and to output a first retimed signal;
• a first amplifier configured to receive the first retimed signal and to output a first weighted signal;
• a second S/H circuit configured to receive the first retimed signal and the clock signal and to output a second retimed signal;
• a second amplifier configured to receive the second retimed signal and to output a second weighted signal;
• a filter configured to receive the second retimed signal and to output a filtered signal;
• a third S/H circuit configured to receive the filtered signal and the clock signal and to output a third retimed signal;
• a third amplifier configured to receive the third retimed signal and to output a third weighted signal;
• and
• a summer configured to combine the first, second, and third weighted signals.