Clock data recovery circuit and display device including the same

A clock data recovery circuit comprising:

• a phase detector configured to output a phase adjustment signal by comparing a clock signal of a first node and an input signal;
• a charge pump configured to adjust a charge amount of a second node according to the phase adjustment signal;
• a first switch, wherein a first terminal of the first switch is electrically connected to the second node, and wherein a second terminal of the first switch is electrically connected to a third node;
• a second switch, wherein a first terminal of the second switch is configured to receive a bias voltage, and wherein a second terminal of the second switch is electrically connected to the third node;
• a capacitor including a first electrode electrically connected to the third node;
• voltage control oscillators respectively including control terminals and respectively including output terminals, wherein each of the control terminals is electrically connected to the third node;
• third switches configured to electrically connect the output terminals, respectively, to the first node;
• and
• a fourth switch, wherein a first terminal of the fourth switch is electrically connected to an output terminal of a voltage control oscillator having a highest frequency band among the voltage control oscillators, and wherein a second terminal of the fourth switch is electrically connected to the first node.

A display device comprising:

• data lines;
• pixels electrically connected to the data lines;
• and
• a data driver configured to supply data voltages to the data lines,
• wherein the data driver includes:
• a clock data recovery circuit configured to receive a clock data signal through a clock data line and configured to generate a clock signal using a clock training pattern in the clock data signal;
• a decoder configured to decode grayscale values in the clock data signal using the clock signal;
• and
• a data voltage generator configured to convert the grayscale values into the data voltages,
• wherein the clock data recovery circuit includes:
• a phase detector configured to output a phase adjustment signal by comparing a clock signal of a first node and an input signal;
• a charge pump configured to adjust a charge amount of a second node according to the phase adjustment signal;
• a first switch, wherein a first terminal of the first switch is electrically connected to the second node, and wherein a second terminal of the first switch is electrically connected to a third node;
• a second switch, wherein a first terminal of the second switch is configured a bias voltage, and wherein a second terminal of the second switch is electrically connected to the third node;
• a capacitor including a first electrode electrically connected to the third node;
• voltage control oscillators respectively including control terminals and respectively including output terminals, wherein each of the control terminals is electrically connected to the third node;
• and
• third switches configured to electrically connect the output terminals, respectively, to the first node.