Semiconductor integrated circuit and reception device

A semiconductor integrated circuit comprising:

• a summer circuit;
• a sampler electrically connected to an output node of the summer circuit;
• a shift register that is electrically connected to an output node of the sampler and includes K stages of registers, K being an integer that is equal to or larger than 3;
• a control circuit to which output nodes of respective registers of N-th to M-th stages among the K stages of registers are electrically connected, N being an integer larger than 1 and smaller than K, M being an integer larger than N and equal to or smaller than K;
• a first switch including one end electrically connected to the output node of the summer circuit;
• and
• a correction circuit including a first control node that is electrically connected to the control circuit through a first feedback line and an output node to which a second end of the first switch is electrically connected.