Method to compensate for metastability of asynchronous SAR within delta sigma modulator loop
AssigneeAnalog Devices, Inc.
InventorAbhishek Bandyopadhyay
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Abstract
Herein disclosed are some examples of metastability detectors and compensator circuitry for successive-approximation-register (SAR) analog-to-digital converters (ADCs) within delta sigma modulator (DSM) loops. A metastability detector may detect metastability at an output of a SAR ADC and compensator circuitry may implement a compensation scheme to compensate for the metastability. The identification of the metastability and/or compensation for the metastability can avoid detrimental effects and/or errors to the DSM loops that may be caused by the metastability of the SAR ADCS.
Claims20
An apparatus for compensating for metastability of a successive-approximation-register (SAR) analog-to-digital converter (ADC), comprising:
- a metastability detector coupled to the SAR ADC, the metastability detector to detect the metastability of the SAR ADC and output an indication that metastability of the SAR ADC has been detected;
- and
- compensator circuitry coupled to the metastability detector, the compensator circuitry to implement a compensation scheme in response to the indication that metastability of the SAR ADC has been detected by the metastability detector;
- wherein the compensation scheme includes:
- (1) detecting metastability at a bit trial corresponding to an Nth bit position of a current sample, N being a position counting from a most significant bit of the current sample;
- (2) storing a truncated value of a preceding sample having N most significant bits of the preceding sample;
- (3) applying the truncated value to a capacitor digital-to-analog converter of the SAR ADC;
- and
- (4) continuing with remaining bit trails for the current sample with the truncated value applied to complete conversion of the current sample.
A delta sigma modulator (DSM) loop, comprising:
- an asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC), wherein conversion by the asynchronous SAR ADC is triggered by an ADC clock;
- a metastability detector coupled to the asynchronous SAR ADC, the metastability detector to detect metastability of the asynchronous SAR ADC;
- and
- compensator circuitry coupled to the metastability detector, wherein the compensator circuitry is to implement a compensation scheme in response to the metastability detector detecting metastability of the asynchronous SAR ADC;
- wherein the compensation scheme includes:
- (1) detecting metastability at a bit trial corresponding to an Nth bit position of a current sample, N being a position counting from a most significant bit of the current sample;
- (2) storing a truncated value of a preceding sample having N most significant bits of the preceding sample;
- (3) applying the truncated value to a capacitor digital-to-analog converter of the SAR ADC;
- and
- (4) continuing with remaining bit trails for the current sample with the truncated value applied to complete conversion of the current sample.
A method of compensating for metastability of an asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC), comprising:
- detecting, by a metastability detector, metastability of the asynchronous SAR ADC;
- detecting, by compensator circuitry coupled to the metastability detector, that the metastability detector has detected metastability of the asynchronous SAR ADC;
- and
- implementing, by the compensator circuitry, a compensation scheme in response to detection that the metastability detector has detected metastability of asynchronous SAR ADC;
- wherein implementing the compensation scheme includes:
- (1) detecting metastability at a bit trial corresponding to an Nth bit position of a current sample, N being a position counting from a most significant bit of the current sample;
- (2) storing a truncated value of a preceding sample having N most significant bits of the preceding sample;
- (3) applying the truncated value to a capacitor digital-to-analog converter of the SAR ADC;
- and
- (4) continuing with remaining bit trails for the current sample with the truncated value applied to complete conversion of the current sample.
Dependencies are inferred from the claim text.