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US 11,539,369 B2Granted
Duty-cycle corrector circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorWeiShuo Lin
Life of this patent
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Abstract
A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.
Claims20
A duty-cycle (DC) corrector circuit, comprising:
- a delay-locked loop (DLL) circuit;
- and
- a duty-cycle correction (DCC) circuit operably connected to the DLL circuit, wherein:
- the DCC circuit comprises:
- a duty adjusting (DA) circuit operable to receive a clock_in signal and output a delayed first signal, the DA circuit further operable to adjust a duty cycle of the delayed first signal based on receipt of a duty control signal;
- a pulse generator (PG) circuit operably connected to the DA circuit, the PG circuit operable to receive the delayed first signal and a delayed second signal and output a first pulse signal and a second pulse signal;
- and
- a duty corrector (DC) circuit operably connected to the PG circuit, the DC circuit operable to receive the first pulse signal and the second pulse signal from the PG circuit and, based on signal levels of the first and the second pulse signals, output a duty control signal that is received by the DA circuit and used to adjust the duty cycle of the delayed first signal;
- and
- the DLL circuit comprises:
- a phase detector (PD) circuit operable to receive the delayed first signal and the delayed second signal and to detect a phase difference between the delayed first and the second signals;
- an inverter circuit operable to receive the delayed first signal and output a second signal;
- and
- a variable delay circuit operably connected between the PD circuit and the inverter circuit, the variable delay circuit operable to adjust a delay of the second signal to produce the delayed second signal, the adjustment of the delay of the second signal adjusting a delay between the delayed first signal and the delayed second signal.
11 more elements
An electronic device, comprising:
- a duty-cycle (DC) corrector circuit comprising:
- a delay-locked loop (DLL) circuit;
- and
- a duty-cycle correction (DCC) circuit operably connected to the DLL circuit, wherein:
- the DCC circuit comprises:
- a duty adjusting (DA) circuit operable to receive a clock_in signal and output a delayed first signal, the DA circuit further operable to adjust a duty cycle of the delayed first signal based on receipt of a duty control signal;
- a pulse generator (PG) circuit operably connected to the DA circuit, the PG circuit operable to receive the delayed first signal and a delayed second signal and output a first pulse signal and a second pulse signal;
- and
- a duty corrector (DC) circuit operably connected to the PG circuit, the DC circuit operable to receive the first pulse signal and the second pulse signal from the PG circuit and, based on signal levels of the first and the second pulse signals, output a duty control signal that is received by the DA circuit and used to adjust the duty cycle of the delayed first signal;
- and
- the DLL circuit comprises:
- a phase detector circuit operable to receive the delayed first signal and the delayed second signal and to detect a phase difference between the delayed first and the second signals;
- an inverter circuit operable to receive the delayed first signal and output a second signal;
- and
- a variable delay circuit operably connected between the phase detector circuit and the inverter circuit, the variable delay circuit operable to adjust a delay of the second signal to produce the delayed second signal, the adjustment of the delay of the second signal adjusting a delay between the delayed first signal and the delayed second signal.
12 more elements
A method comprising:
- receiving a clock_in signal;
- producing a delayed clock_in signal as a delayed first signal;
- inverting the delayed first signal to produce a second signal;
- adjusting a delay of the second signal to produce a delayed second signal, wherein adjusting the delay reduces a phase difference between the delayed first signal and the delayed second signal and the delay is adjusted until the phase difference equals or substantially equals a first given value;
- and
- adjusting a first duty cycle of the delayed first signal and a second duty cycle of the delayed second signal until the first and the second duty cycles equal or substantially equal a second given value.
3 more elements
Dependencies are inferred from the claim text.