Majority logic gate with input paraelectric capacitors

An apparatus comprising:

• a node;
• a first capacitor having a first terminal to receive a first input, and a second terminal coupled to the node;
• a second capacitor having a first terminal to receive a second input, and a second terminal coupled to the node;
• a third capacitor having a first terminal to receive a third input, and a second terminal coupled to the node, wherein the first capacitor, the second capacitor and the third capacitor comprise a room temperature paraelectric material;
• and
• a logic having an input and an output, wherein the input of the logic is coupled to the node, and wherein the input of the logic has capacitance.

A system comprising:

• a memory;
• a processor circuitry to execute one or more instructions;
• and
• a communication interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes:
• a node;
• a first capacitor having a first terminal to receive a first input, and a second terminal coupled to the node;
• a second capacitor having a first terminal to receive a second input, and a second terminal coupled to the node;
• a third capacitor having a first terminal to receive a third input, and a second terminal coupled to the node, wherein the first capacitor, the second capacitor and the third capacitor comprise a non-linear material;
• and
• a logic having an input and an output, wherein the input of the logic is coupled to the node, wherein the input of the logic has capacitance, and wherein the processor circuitry comprising:
• a first transistor coupled to the node and ground, wherein the first transistor is controllable by a first control;
• and
• a second transistor coupled to the input of the logic and the ground, wherein the second transistor is controllable by a second control.