Systems and methods for generating a controllable-width pulse signal
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsRuey-Bin Sheen, Ming Hsien Tsai, Chih-Hsien Chang, Tsung-Hsien Tsai
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Abstract
Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.
Claims20
A circuit for generating a pulse output having a controllable pulse width, comprising:
- a delay line having a plurality of stages;
- a replica delay line having stages substantially similar to the delay line;
- a delay per stage calculation circuit configured to determine a per-stage delay of the delay line using a first clock input and a sampling clock input;
- a pulse generation circuit configured to generate the pulse output by using the delay line and based on the per-stage delay;
- wherein the delay line receives a second clock input;
- wherein the delay per stage calculation circuit determines the per-stage delay of the delay line based on operation of the replica delay line receiving the first clock input.
A method of generating a pulse output having a controllable pulse width, comprising:
- accessing a delay line having a plurality of stages;
- providing a first clock input to a replica delay line having stages substantially similar to the delay line,
- sampling an output of the replica delay line using a sampling clock input,
- determining a per-stage delay of the delay line based on operation of the replica delay line;
- and
- generating the pulse output using the delay line based on the per-stage delay by providing the delay line a second clock input.
A circuit for generating a pulse output having a controllable pulse width, comprising:
- a delay line having a plurality of stages;
- a delay per stage calculation circuit configured to determine a per-stage delay of the delay line using a sampling clock input;
- a pulse generation circuit configured to generate the pulse output by using the delay line and based on the per-stage delay;
- wherein the delay line receives a fast clock input;
- wherein the delay per stage calculation circuit determines the per-stage delay of the delay line based on operation of the delay line receiving the fast clock input;
- wherein the delay per stage calculation circuit comprises:
- a time-to-digital converter configured to sample an output of the delay line according to the sampling clock input;
- and a period stage calculator configured use the sampled output of the delay line to determine a number of sampling clock periods are in a cycle of the sampled output of the delay line.
Dependencies are inferred from the claim text.