Systems and methods for generating a controllable-width pulse signal
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsRuey-Bin Sheen, Ming Hsien Tsai, Chih-Hsien Chang, Tsung-Hsien Tsai
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Abstract
Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.
Claims20
A circuit for generating a pulse output having a controllable pulse width, comprising:
- a delay line having a plurality of stages;
- a delay per stage calculation circuit configured to determine a per-stage delay of the delay line;
- a pulse generation circuit configured to generate the pulse output by using the delay line and based on the per-stage delay;
- wherein the pulse generation circuit selectively accesses outputs of two of the plurality of stages of the delay line based on the per-stage delay and a selected pulse width to generate the pulse output.
A method of generating a pulse output having a controllable pulse width, comprising:
- determining a per-stage delay of a delay line based on a first clock input;
- generating the pulse output using the delay line based on the per-stage delay by providing the delay line a second clock input, the second clock input having a lower frequency than the first clock input
- generating the pulse output from the frequency of the second clock input, wherein the frequency of the second clock input is substantially lower than the frequency of the first clock frequency used to determine the per-stage delay.
A circuit for generating a pulse output having a pulse width of a controllable length of time, comprising:
- a delay line and a replica delay line each having a plurality of stages;
- a delay per stage calculation circuit configured to determine a per-stage delay of the delay line by using a first clock input, wherein the determining a per-stage delay of the delay line is based on operation of the replica delay line;
- a pulse generation circuit configured to generate the pulse output by using the delay line and based on the per-stage delay, wherein the delay line receives a second clock input.
Dependencies are inferred from the claim text.