Open loop reactance matching circuitry

A circuit comprising:

• an Open Loop Reactance Matching Circuit Control Signal Generator (OLRMCCSG);
• and
• an Open Loop Reactance Matching Circuit (OLRMC), wherein the OLRMC is coupled to the OLRMCCSG, wherein the OLRMC generates a reactance matching voltage or a reactance matching current, wherein the reactance matching voltage is phase delayed with respect to an input voltage, wherein the reactance matching current is phase delayed with respect to an input current, wherein the OLRMC comprises a first transistor and a second transistor, wherein the OLRMCCSG generates a first control signal that controls a gate of the first transistor, wherein the OLRMCCSG generates a second control signal that controls a gate of the second transistor, wherein the first control signal is phase shifted ninety-degrees with respect to either the input voltage or the input current, and wherein the second control signal is phase shifted ninety-degrees with respect to either the input voltage or the input current.

A circuit comprising:

• an Open Loop Reactance Matching Circuit Control Signal Generator (OLRMCCSG);
• and
• an Open Loop Reactance Matching Circuit (OLRMC), wherein the OLRMC is coupled to the OLRMCCSG, wherein the OLRMC generates a reactance matching voltage or a reactance matching current, wherein the reactance matching voltage is phase delayed with respect to an input voltage, wherein the reactance matching current is phase delayed with respect to an input current, wherein the OLRMCCSG receives amplifier control signals output by an amplifier controller and generates control signals that are ninety degree phase shifted with respect to the amplifier control signals, and wherein the generated control signals are supplied to the OLRMC and the generated control signals control switching of transistors in the OLRMC.

A method comprising:

• coupling an Open Loop Reactance Matching Circuit (OLRMC) to a load and to a supply;
• and
• controlling the OLRMC to generate either a reactance matching voltage or a reactance matching current, wherein if the reactance matching voltage is generated, then the reactance matching voltage has a phase that is delayed as compared to a phase of an input voltage, wherein if the reactance matching current is generated, then the reactance matching current has a phase that is delayed as compared to a phase of an input current, wherein the OLRMC comprises a first transistor and a second transistor, wherein the OLRMCCSG generates a first control signal that controls a gate of the first transistor, wherein the OLRMCCSG generates a second control signal that controls a gate of the second transistor, wherein the first control signal is phase shifted ninety-degrees with respect to either the input voltage or the input current, and wherein the second control signal is phase shifted ninety-degrees with respect to either the input voltage or the input current.