Timing circuit for locking a voltage controlled oscillator to a high frequency by use of low frequency quotients and resistor to switched capacitor matching

A circuit comprising:

• a voltage controlled oscillator (VCO);
• a reference circuit;
• an integrator including an op-amp including:
• an inverting node,
• a non-inverting node coupled to the reference circuit, and
• an output node coupled to the VCO, and
• an integrator capacitor coupled to the non-inverting node and the output node;
• a switched capacitor resistor circuit (SCRC) including:
• a first switch,
• a second switch, and
• a switched capacitor coupled to the first switch and the second switch,
• the switched capacitor being selectively coupled:
• at a top terminal, to a ground potential or a supply voltage using the first switch;
• at a bottom terminal, to the inverting node or to the reference circuit using the second switch;
• and
• a discharge resistor coupled between the ground potential and the inverting node,
• wherein charging and discharging of the integrator capacitor results in the integrator generating an integrated signal used to generate a control signal provided to the VCO, the VCO is locked to and outputs a high frequency signal based on the control signal.

A method, of controlling a voltage controlled oscillator to a high frequency, comprising:

• generating a low frequency signal based on a high frequency signal;
• wherein the high frequency signal is generated by the voltage controlled oscillator;
• selectively generating inverting signals, using a switched capacitor resistor circuit referenced to a first reference voltage of a reference circuit, based on the low frequency signal;
• and
• generating, based on the inverting signals, a control signal used to control the voltage controlled oscillator, the control signal being generated based on a second reference voltage from the reference circuit, the first reference voltage and the second reference voltage being between a supply voltage and a ground potential.