Driver circuit for full-bridge DC motor driver system

A motor-drive circuit comprising:

• a first high-side transistor having a first control terminal and coupled between a voltage supply terminal and a first output adapted to be coupled to a motor;
• a second high-side transistor having a second control terminal and coupled between the voltage supply terminal and a second output adapted to be coupled to the motor;
• a first low-side transistor coupled between the first output and a ground terminal;
• a second low-side transistor coupled between the second output and the ground terminal;
• a first switch having a first terminal coupled to the voltage supply terminal and a second terminal coupled to the first control terminal, the first switch operable to connect the voltage supply terminal to the first control terminal responsive to receiving a voltage supply enable signal;
• a second switch having a first terminal coupled to a charge pump terminal and a second terminal coupled to the first control terminal, the second switch operable to couple the charge pump terminal to the first control terminal responsive to receiving a charge pump enable signal;
• and
• a comparison circuit having a first terminal coupled to the first control terminal and a second terminal coupled to the voltage supply terminal, the comparison circuit operable to provide the voltage supply enable signal when the voltage at the first control terminal is lower than a supply voltage and to provide the charge pump enable signal when the voltage at the first control terminal is higher than the supply voltage.

A driver circuit for driving a high-side transistor that has a high-side gate, the driver circuit comprising:

• a first switch having a first terminal coupled to a voltage supply terminal, a second terminal coupled to the high-side gate, and a third terminal;
• a second switch having a first terminal coupled to a charge pump terminal, a second terminal coupled to the high-side gate, and a third terminal;
• a first PFET having a source coupled to the charge pump terminal, a drain, and a gate;
• a first NFET having a drain coupled to the source drain of the first PFET, a source coupled to the voltage supply terminal, and a gate coupled to the gate of the first PFET;
• a resistor coupled between the charge pump terminal and the gate of the first PFET;
• a buffer having an input coupled to the drain of the first PFET and an output coupled to the third terminal of the second switch;
• a source follower PFET having a source coupled to the gate of the first PFET, a gate coupled to the voltage supply terminal, and a drain;
• a diode coupled between the drain of the source follower PFET and the high-side gate;
• and
• a level shifter having an input coupled to the output of the buffer circuit and an output coupled to the third terminal of the first switch.