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US 11,539,313 B2Granted
System and method of synchronizing a switching signal
AssigneeInfineon Technologies AG
InventorsJens Barrenscheen, Matthias Bogus, Christian Heiling
Life of this patent
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Abstract
In accordance with an embodiment, a method includes generating a clock signal; generating a switching signal based on the clock signal; generating a synchronization signal having an edge transition corresponding to a predetermined phase of the switching signal; transmitting the synchronization signal to a master controller; receiving a frequency adjustment command from the master controller based on the transmitted synchronization signal; and adjusting a frequency of the clock signal based on the frequency adjustment command.
Claims24
A method comprising:
- generating, by a slave controller, a clock signal;
- generating, by the slave controller, a switching signal based on the clock signal;
- generating, by the slave controller, a synchronization signal having an edge transition corresponding to a predetermined phase of the switching signal;
- transmitting, by the slave controller, the synchronization signal to a master controller, wherein the master controller is external to the slave controller;
- receiving, by the slave controller, a frequency adjustment command from the master controller based on the transmitted synchronization signal;
- adjusting, by the slave controller, a frequency of the clock signal based on the frequency adjustment command received from the master controller, wherein:
- the frequency adjustment command comprises a first frequency adjustment command and a second frequency adjustment command;
- and adjusting the frequency of the clock signal comprises
- increasing the frequency of the clock signal by a first predetermined amount upon receipt of the first frequency adjustment command, and
- decreasing the frequency of the clock signal by a second predetermined amount upon receipt of the second frequency adjustment command;
- performing, by a timing analysis circuit of the master controller having a first input coupled to a synchronization signal output of the slave controller and a first output coupled to a first interface of a communications interface circuit of the slave controller, and a second input configured to be coupled to a synchronization signal output of a further slave controller and a second output configured to be coupled to a first interface of a communications interface circuit of the further slave controller, a first comparison of a timing of a signal at the first input of the timing analysis circuit with a timing of a reference timing signal,
- producing, by the timing analysis circuit, the first frequency adjustment command and the second frequency adjustment command at the first output based on the first comparison,
- performing, by the timing analysis circuit, a second comparison of a timing of a signal at the second input of the timing analysis circuit with the timing of the reference timing signal;
- and
- generating, by the timing analysis circuit, the first frequency adjustment command and the second frequency adjustment command at the second output based on the second comparison.
12 more elements
A system comprising:
- a first slave circuit comprising:
- a clock generator comprising a clock signal output and a frequency control input, the clock generator configured to produce a clock signal at the clock signal output based on a signal received at the frequency control input;
- a drive signal generator having a clock signal input coupled to the clock signal output of the clock generator, a drive signal output configured to be coupled to a switching circuit, and a synchronization signal output configured to be coupled to a master controller external to the first slave circuit, the drive signal generator configured to produce a drive signal at the drive signal output based on the clock signal, and a synchronization signal at the synchronization signal output, the synchronization signal having an edge transition corresponding to a predetermined phase of the drive signal;
- and
- a communications interface circuit comprising a first interface configured to be coupled to the master controller, and a second interface configured to be coupled to the frequency control input of the clock generator, the communications interface circuit configured to
- increase a frequency of the clock signal via the frequency control input after receiving a first command from the master controller based on the synchronization signal, and
- decrease a frequency of the clock signal via the frequency control input after receiving a second command from the master controller based on the synchronization signal, wherein:
- the master controller comprises a timing analysis circuit having a first input coupled to the synchronization signal output of the first slave circuit and a first output coupled to the first interface of the communications interface circuit of the first slave circuit,
- the timing analysis circuit is configured to perform a first comparison of a timing of a signal at the first input of the timing analysis circuit with a timing of a reference timing signal,
- the timing analysis circuit is configured to produce the first command and the second command at the first output based on the first comparison,
- the timing analysis circuit further comprises a second input configured to be coupled to a synchronization signal output of a second slave circuit and a second output configured to be coupled to a first interface of a communications interface circuit of the second slave circuit;
- the timing analysis circuit is further configured to perform a second comparison of a timing of a signal at the second input of the timing analysis circuit with the timing of the reference timing signal;
- and
- the timing analysis circuit is further configured to generate the first command and the second command at the second output based on the second comparison.
11 more elements
Dependencies are inferred from the claim text.