Snapback electrostatic discharge protection for electronic circuits

An electrostatic discharge (ESD) protection circuit comprising:

• a trigger circuit connected to an IO pad and a reference voltage node, the trigger circuit configured to detect an ESD event at the IO pad;
• a fail-safe protection circuit connected to the IO pad, the trigger circuit, a supply voltage, and the reference voltage node, the fail-safe protection circuit configured to manage a voltage level for the reference voltage node to enable a voltage level at the IO pad to rise to a predetermined threshold when the supply voltage is substantially zero;
• and
• a gate bias circuit connected to the reference voltage node, the supply voltage, a ground source, a first gate node connected to a first gate terminal of a first transistor, and a second gate node connected to a second gate terminal of a second transistor, the gate bias circuit configured to dynamically control a voltage level for the first gate node and the second gate node.

A control bus of a memory die comprising:

• a trigger circuit connected to an IO pad and a reference voltage node, the trigger circuit configured to detect an ESD event at the IO pad by way of a first resistor and a first capacitor each configured to charge the first capacitor within a first time constant less than 10 nanoseconds;
• a fail-safe protection circuit connected to the IO pad, the trigger circuit, a supply voltage, and the reference voltage node, the fail-safe protection circuit configured to manage a voltage level for the reference voltage node to enable a voltage level at the IO pad to rise to a fail-safe voltage threshold when the supply voltage is substantially zero, the fail-safe protection circuit comprising a second resistor and a second capacitor each configured to charge the second capacitor within a second time constant greater than the first time constant;
• and
• a gate bias circuit connected to the reference voltage node, the supply voltage, a ground source, a first gate node connected to a first gate terminal of a first transistor, and a second gate node connected to a second gate terminal of a second transistor, the gate bias circuit configured to dynamically control a voltage level for the first gate node and the second gate node.