Display substrate and manufacturing method thereof, display panel

A manufacturing method of a display substrate, comprising:

• forming a gate driver-on-array circuit on a base substrate, wherein the base substrate is divided into a display region and a peripheral region, the gate driver-on-array circuit is provided in the peripheral region, the peripheral region comprises a transistor region and a capacitor region located on a side of the transistor region away from the display region, the gate driver-on-array circuit comprises a plurality of transistors and a plurality of capacitors, all of the plurality of transistors are provided in the transistor region, at least a part of the plurality of capacitors are provided in the capacitor region;
• forming an encapsulation structure to encapsulate the display region and the transistor region;
• and
• providing in a sealing region a sealing structure for encapsulating the capacitors in the capacitor region, wherein the sealing region is provided on a side of the encapsulation structure away from the display region;
• wherein prior to the step of forming the encapsulation structure, the manufacturing method further comprises forming a protection layer on the plurality of transistors,
• wherein the step of the forming the encapsulation structure to encapsulate the display region and the transistor region comprises:
• encapsulating the display region and the plurality of transistors in the transistor region and the protection layer;
• wherein the step of forming the gate driver-on-array circuit on the base substrate further comprises:
• forming at least one first signal line and at least one second signal line on the base substrate, the at least one first signal line is provided in a first lead region located on a side of the capacitor region of the sealing region away from the display region, and the at least one second signal line is provided in a second lead region located between the transistor region and the display region, and
• the step of forming the encapsulation structure to encapsulate the display region and the transistor region comprises:
• encapsulating the display region and the plurality of transistors in the transistor region, the at least one second signal line in the second lead region and the protection layer;
• and
• the step of providing in the sealing region the sealing structure for encapsulating the capacitors in the capacitor region comprises:
• providing in the sealing region the sealing structure for encapsulating the capacitors in the capacitor region and the at least one first signal line in the first lead region,
• wherein the at least one first signal line is a clock signal line, and the at least one second signal line is a voltage signal line.