3-D crossbar architecture for fast energy-efficient in-memory computing of graph transitive closure
AssigneeUniversity of Central Florida Research Foundation, Inc.
InventorsAlvaro Velasquez, Sumit Kumar Jha
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Abstract
An in-memory computing architecture is disclosed that can evaluate the transitive closure of graphs using the natural parallel flow of information in 3-D nanoscale crossbars. The architecture can be implemented using 3-D crossbar architectures with as few as two layers of 1-diode 1-resistor (1D1R) interconnects. The architecture avoids memory-processor bottlenecks and can hence scale to large graphs. The approach leads to a runtime complexity of O(n2) using O(n2) memristor devices. This compares favorably to conventional algorithms with a time complexity of O((n3)/p+(n2) log p) on p processors. The approach takes advantage of the dynamics of 3-D crossbars not available on 2-D crossbars.
Claims5
A computer-implemented method for simulating operation of a physical system having a plurality of physical subsystems, for computing a transitive closure of a directed graph, G, comprising:
- implementing a Boolean circuit model of a 3D crossbar memory for in-memory parallel computation of a matrix X based on the directed graph G,
- wherein the Boolean circuit model of the 3D crossbar memory consists of at least two layers of memory cells, each memory cell being in a binary state of 1, describing a low-resistance state, or a binary state of 0, describing a high-resistance state,
- wherein the Boolean circuit model includes a topmost set of row wires where voltages are applied to read the binary state of the memory cells,
- wherein a memory cell with a binary state of 1 permits a high current to be redirected between two connected wires and a memory cell with a binary state of 0 inhibits current from one connected wire to another connected wire,
- wherein a first layer of memory cells connect the topmost row wires to column wires,
- wherein a second layer of memory cells connect the column wires with a set of bottommost row wires,
- wherein the bottommost row wires are connected to the topmost row wires via feedback loops and,
- wherein the Boolean circuit model having at least one external feedback loop;
- for each row in the matrix, performing repeated Boolean matrix multiplication of the matrix X so as to generate a converged wire vector associated with the given row in the matrix;
- combining the converged wire vectors to generate a transitive closure matrix X*;
- and
- outputting the transitive closure matrix X*.
Dependencies are inferred from the claim text.