US 11,538,939 B2 · Controlled bottom junctions

Abstract

A method of forming a vertical transport field effect transistor (VTFET) is provided. The method includes forming one or more vertical fins on a substrate, wherein there is a fin transition region between each of the one or more vertical fins and the substrate. The method further includes forming a sidewall liner having a first thickness on each of the one or more vertical fins. The method further includes forming a sidewall spacer having a second thickness on each of the sidewall liner(s), wherein the first thickness of the sidewall liner and the second thickness of the sidewall spacer determines an offset distance from each of the one or more vertical fins. The method further includes forming a trench with an edge offset from each of the one or more vertical fins by the offset distance.

Claims12

Dependent claims

A vertical transport field effect transistor (VTFET), comprising:

a vertical fin on a substrate;
a fin transition region between the vertical fin and the substrate, wherein the fin transition region has a curved surface;
a gap layer segment on the substrate;
a bottom spacer layer on the gap layer segment;
a gate dielectric layer on a sidewall of the vertical fin, a top surface of the bottom spacer layer, at least a portion of the gap layer segment, and the fin transition region, wherein the gate dielectric layer separates the bottom spacer layer and an edge of the gap layer segment from the fin transition region;
and
a conductive gate layer on the gate dielectric layer.

4 more elements

Dependencies are inferred from the claim text.

Controlled bottom junctions

Life of this patent

Controlled bottom junctions

Life of this patent

Abstract

Claims12