Silicon carbide semiconductor device

A silicon carbide semiconductor device including a cell region having a main cell region and a sense cell region being electrically isolated by an element isolation portion, the silicon carbide semiconductor device comprising:

• a substrate made of silicon carbide and having either a first conductivity type or a second conductivity type;
• a first impurity region disposed on a surface of the substrate, the first impurity region having the first conductivity type and having a lower impurity concentration than the substrate;
• a first current dispersion layer made of silicon carbide and having the first conductivity type, the first current dispersion layer disposed on the first impurity region;
• a plurality of first deep layers made of silicon carbide and having the second conductivity type, the first deep layers disposed above the first impurity region, each of the first deep layers and the first current dispersion layer disposed alternately with respect to a plane direction of the substrate:
• a second current dispersion layer made of silicon carbide and having the first conductivity type, the second current dispersion layer disposed on the first current dispersion layer and the first deep layers, and connected to the first current dispersion layer;
• a second deep layer made of silicon carbide and having the second conductivity type, the second deep layer disposed on the first current dispersion layer and the first deep layers, and connected to the first deep layers;
• a base region made of silicon carbide and having the second conductivity type, the base region disposed on the second current dispersion layer and the second deep layer, and connected to the second deep layers;
• a trench gate structure including a trench, a gate insulation film, and a gate electrode, the trench extending along a direction as a longitudinal direction and disposed to be deeper than the base region, the gate insulation film disposed at an inner wall surface of the trench, and the gate electrode disposed on the gate insulation film inside the trench;
• a second impurity region made of silicon carbide and having the first conductivity type, and being in contact with the trench gate structure at a surface layer portion of the base region;
• and
• a plurality of first electrodes separately provided in the sense cell region and the main cell region, the first electrodes electrically connected to the second impurity region at the main cell region and the second impurity region at the sense cell region, respectively, and electrically connected to the base region;
• and
• a second electrode disposed at a rear surface of the substrate, and electrically connected to the substrate,
• wherein the first current dispersion layer, the first deep layers, the second current dispersion layer, the second deep layer, the base region, and the trench gate structure are disposed at the cell region and the element isolation region,
• wherein the second impurity region, the first electrodes, and the second electrode are disposed at the main cell region and the sense cell region to form a vertical semiconductor element at each of the main cell region and the sense cell region,
• wherein the vertical semiconductor element is configured to allow a current flowing between the first electrode and the second electrode through a voltage applied to the gate electrode,
• wherein, at the element isolation portion, the first deep layers are disposed at both sides of the trench gate structure and are separated with a spacing interval, and
• wherein the spacing interval between the first deep layers at the element isolation portion is shorter than or equal to a spacing interval between the first deep layers at the main cell region.