Nanostructures and method for manufacturing the same

A method, comprising:

• forming a first plurality of channel members over a first region of a substrate, the first plurality of channel members being vertically stacked;
• forming a second plurality of channel members over a second region of a substrate, the second plurality of channel members being vertically stacked;
• forming an isolation feature in the first and second regions, wherein a top surface of the isolation feature is higher in the second region than in the first region, such that a portion of the second plurality of channel members is below the top surface of the isolation feature in the second region;
• forming a first gate structure engaging the first plurality of channel members, thereby forming a first transistor in the first region;
• forming a second gate structure engaging the second plurality of channel members, thereby forming a second transistor in the second region;
• and
• removing the portion of the second plurality of channel members from the second region, such that a number of the first plurality of channel members in the first transistor is larger than a number of the second plurality of channel members in the second transistor.

A semiconductor device, comprising:

• a first gate structure engaging a first plurality of channel members;
• a second gate structure engaging a second plurality of channel members;
• a first backside dielectric feature disposed directly under the first gate structure;
• and
• a second backside dielectric feature disposed directly under the second gate structure,
• wherein a number of the first plurality of channel members is larger than a number of the second plurality of channel members.