Method for increasing an oxide thickness at trench corner of an U-shaped gate metal-oxide-semiconductor field-effect transistor

A method for increasing an oxide thickness at trench corner of an U-shaped gate metal-oxide-semiconductor field-effect transistor (UMOSFET), comprising:

• providing an N-type semiconductor substrate and forming an N-type drift region on the N-type semiconductor substrate;
• forming an N-type heavily doped region in the N-type drift region;
• forming a first P-type heavily doped region, a second P-type heavily doped region respectively on opposite sides of the N-type heavily doped region, and a P-type body region between the N-type heavily doped region, the first P-type heavily doped region, the second P-type heavily doped region and the N-type drift region;
• depositing an etch hardmask layer on the N-type heavily doped region, the first P-type heavily doped region and the second P-type heavily doped region, and using a lithography process to form a trench, wherein the trench comprises two opposite sidewalls and a bottom, and an right angle is formed between each of the two opposite sidewalls and the bottom;
• forming a pad oxide along the two opposite sidewalls and the bottom of the trench;
• providing an oxidation barrier on the pad oxide and performing a thermal oxidation process, wherein the N-type semiconductor substrate is made of an N-type silicon carbide, the N-type silicon carbide adjacent to the right angle of the trench is oxidized to form a corner oxide by the thermal oxidation process, and wherein an oxidation rate of the two opposite sidewalls of the trench is greater than that of the bottom of the trench, such that the right angle of the trench is turned to be smooth due to a formation of the corner oxide;
• removing the pad oxide and the oxidation barrier and performing a gate oxide forming process to generate a gate oxide, wherein the gate oxide is formed along the two opposite sidewalls and the bottom of the trench and in connection with the corner oxide;
• forming a gate conductive layer in the trench and further depositing a dielectric layer on the gate conductive layer;
• and
• forming at least one contact window which extends through the dielectric layer and the etch hardmask layer, and electrically connected to the N-type heavily doped region, the first P-type heavily doped region, and the second P-type heavily doped region for providing electrical paths.