US 11,538,916 B2Granted

Semiconductor device

AssigneeSamsung Electronics Co., Ltd.

InventorsYoontae Hwang, Wandon Kim, Geunwoo Kim, Heonbok Lee, Taegon Kim, Hanki Lee

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Abstract

A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

Claims20

Dependent claims

A semiconductor device, comprising:

a substrate;
a fin active region on the substrate and extending in a first direction, the first direction being parallel to an upper surface of the substrate;
a gate structure extending across the fin active region and extending in a second direction, the second direction being different from the first direction and parallel to the upper surface of the substrate;
a source/drain region in the fin active region on at least one side of the gate structure;
an insulating structure covering the gate structure and the source/drain region;
and
a first contact structure and a second contact structure penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure,
wherein at least one of the first contact structure and the second contact structure includes:
a seed layer on at least one of the gate structure and the source/drain regions, the seed layer including a lower region and an upper region, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and
a contact plug on an upper region of the seed layer and having a second grain size.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/231,126Filed 15 Apr 2021
Priority: KR 10-2020-01110531 Sep 2020
Published: US 2022/0069100 A13 Mar 2022
Granted: 27 Dec 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification28 codes

H10D 64/62
Electrodes characterised by their materials: electrodes ohmically coupled to a semiconductor
H10D 30/0191
Of FETs having stacked nanowire, nanosheet or nanoribbon channels: forming stacked channels, e.g. changing their shapes or sizes
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/43
FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels: having one-dimensional [1D] charge…