US 11,538,904 B2Granted

Semiconductor device

AssigneeRohm Co., Ltd.

InventorsYuto Osawa, Toshio Nakajima, Shuta Kojima

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Abstract

Disclosed is a semiconductor device including a semiconductor layer having a main surface, a first conductivity type drift region formed at a surface layer part of the main surface, a super junction region having a first conductivity type first column region and a second conductivity type second column region, a second conductivity type low resistance region formed at the surface layer part of the drift region and having an impurity concentration in excess of that of the second column region, a region insulating layer formed on the main surface and covering the low resistance region such as to cause part of the low resistance region to be exposed, a first pad electrode formed on the region insulating layer such as to overlap with the low resistance region, and a second pad electrode formed on the main surface and electrically connected to the second column region and the low resistance region.

Claims19

Dependent claims

A semiconductor device, comprising:

a semiconductor layer having a main surface;
a first conductivity type drift region at a surface layer part of the main surface;
a super junction region having a first conductivity type first column region and a second conductivity type second column region, wherein the first conductivity type first column region and the second conductivity type second column region are in an alternate arrangement at a surface layer part of the first conductivity type drift region;
a second conductivity type field limit region at the surface layer part of the first conductivity type drift region such as to surround the super junction region in a plan view, wherein the second conductivity type field limit region is shallower than the second conductivity type second column region;
a second conductivity type low resistance region at the surface layer part of the first conductivity type drift region, wherein the second conductivity type low resistance region has an impurity concentration in excess of an impurity concentration of the second conductivity type second column region;
a region insulating layer on the main surface, wherein the region insulating layer covers the second conductivity type low resistance region such that a part of the second conductivity type low resistance region is exposed;
a first pad electrode on the region insulating layer, wherein the first pad electrode overlaps with the second conductivity type low resistance region;
and
a second pad electrode on the main surface, wherein
the second pad electrode is electrically connected to the second conductivity type second column region and the second conductivity type low resistance region, and
the first pad electrode is spaced apart from the second pad electrode.

8 more elements

A semiconductor device, comprising:

a semiconductor layer having a main surface;
a first conductivity type drift region at a surface layer part of the main surface;
a super junction region having a first conductivity type first column region and a second conductivity type second column region, wherein the first conductivity type first column region and the second conductivity type second column region are in an alternate arrangement at a surface layer part of the first conductivity type drift region;
a second conductivity type field limit region at the surface layer part of the first conductivity type drift region such as to surround the super junction region in a plan view wherein the second conductivity type field limit region is shallower than the second conductivity type second column region;
a second conductivity type low resistance region in a region surrounded by the second conductivity type field limit region at the surface layer part of the first conductivity type drift region, wherein the second conductivity type low resistance region has an impurity concentration in excess of an impurity concentration of the second conductivity type field limit region;
a region insulating layer on the main surface, wherein the region insulating layer covers the second conductivity type low resistance region such that a part of the second conductivity type low resistance region is exposed;
a first pad electrode on the region insulating layer, wherein the first pad electrode overlaps with the second conductivity type low resistance region;
and
a second pad electrode on the main surface, wherein
the second pad electrode is electrically connected to the second conductivity type second column region and the second conductivity type low resistance region, and
the first pad electrode is spaced apart from the second pad electrode.

8 more elements

A semiconductor device, comprising:

a semiconductor layer having a main surface;
a first conductivity type drift region at a surface layer part of the main surface;
a super junction region having a first conductivity type first column region and a second conductivity type second column region, wherein the first conductivity type first column region and the second conductivity type second column region are in an alternate arrangement at a surface layer part of the first conductivity type drift region;
a second conductivity type low resistance region at the surface layer part of the first conductivity type drift region, wherein the second conductivity type low resistance region has an impurity concentration in excess of an impurity concentration of the second conductivity type second column region;
a region insulating layer on the main surface, wherein the region insulating layer covers the second conductivity type low resistance region such that a part of the second conductivity type low resistance region is exposed;
a first pad electrode on the region insulating layer, wherein the first pad electrode overlaps with the second conductivity type low resistance region;
a second pad electrode on the main surface, wherein the second pad electrode is electrically connected to the second conductivity type second column region and the second conductivity type low resistance region;
and
a field effect transistor structure that includes:
a second conductivity type channel region at a surface layer part of the first conductivity type first column region;
a gate insulating layer in contact with the second conductivity type channel region;
and
a gate electrode that faces the second conductivity type channel region, wherein
the gate insulating layer is between the gate electrode and the second conductivity type channel region,
the first pad electrode is electrically connected to the gate electrode,
the second pad electrode is electrically connected to the second conductivity type channel region, and
the field effect transistor structure is in a region outside of the second conductivity type low resistance region.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/032,224Filed 25 Sep 2020
Priority: JP JP2019-17761327 Sep 2019
Published: US 2021/0098570 A11 Apr 2021
Granted: 27 Dec 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 62/111
Reduced surface field [RESURF] PN junction structures: multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
H10D 30/665
Vertical dmos [vdmos] fets: having edge termination structures
H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 62/051
Manufacture or treatment: forming charge compensation regions, e.g. superjunctions