Semiconductor memory device including variable resistance layer

A semiconductor memory device comprising:

• a first stack structure and a second stack structure each comprising a plurality of insulating layers and a plurality of interconnection layers that are alternately and repeatedly stacked on a substrate;
• an isolation insulating layer disposed between the first and second stack structures;
• and
• a pillar structure disposed between the first and second stack structures and configured to extend through the isolation insulating layer,
• wherein the pillar structure comprises:
• an insulating pillar;
• a first variable resistance layer disposed on the insulating pillar and positioned between the insulating pillar and the first stack structure;
• a second variable resistance layer disposed on the insulating pillar and positioned between the insulating pillar and the second stack structure;
• a first channel layer disposed on the first variable resistance layer and positioned between the first variable resistance layer and the first stack structure
• a second Channel layer disposed on the second variable resistance layer and positioned between the second variable resistance layer and the second stack structure;
• and
• a first gate dielectric layer disposed on the first channel layer and positioned between the first channel layer and the first stack structure;
• and
• a second gate dielectric layer disposed on the second channel layer and positioned between the second channel layer and the second stack structure,
• wherein the isolation insulating layer directly contacts the first and second stack structures and the pillar structure and extends through the first and second stack structures and the pillar structure in the vertical direction.