Memory device, method of forming the same, and memory array

A method of forming a memory device, comprising:

• forming a transistor on a substrate;
• forming an interconnect structure on the transistor;
• and
• forming a memory cell in the interconnect structure, wherein the memory cell comprises:
• a selector, electrically coupled to a source of the transistor;
• a magnetic tunnel junction (MTJ) structure, formed on the selector and electrically coupled to a drain of the transistor;
• and
• a spin orbit torque (SOT) layer, formed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector, wherein the transistor is configured to control a write signal traveling across the SOT layer and the selector, and control a read signal traveling across the SOT layer and the MTJ structure.

A memory array, comprising:

• a plurality of memory cells, wherein each memory cell comprises:
• a selector, a magnetic tunnel junction (MTJ) structure, and a spin orbit torque (SOT) layer disposed between the selector and the MTJ structure;
• a plurality of transistors arranged as an array having a plurality of columns and a plurality of rows, wherein the plurality of transistors have a plurality of drains respectively electrically coupled to a plurality of MTJ structures of the plurality of memory cells;
• a plurality of bit lines respectively electrically coupled to a plurality of SOT layers of the plurality of memory cells;
• a plurality of word lines respectively electrically coupled to a plurality of gates of the plurality of transistors;
• and
• a plurality of source lines respectively electrically coupled to a plurality of sources of the plurality of transistors and a plurality of selectors of the plurality of memory cells, wherein one of the plurality of transistors is configured to control a write signal and a read signal of a corresponding memory cell.