Chip scale package structures
AssigneeIndustrial Technology Research Institute
InventorsYu-Min Lin, Tao-Chih Chang
Life of this patent
Estimating the term…
Abstract
A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a plurality of through silicon via (TSV) and a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.
Claims17
A chip scale package structure, comprising:
- an image sensor chip comprising a first redistribution layer comprising a first conductive wire and a first conductive pad formed on the first conductive wire, wherein the first conductive pad is exposed from a surface of the first redistribution layer;
- a chip comprising a plurality of through silicon via (TSV) and a second redistribution layer comprising a second conductive wire and a second conductive pad formed on the second conductive wire, wherein the plurality of through silicon via (TSV) extend from the second redistribution layer to a surface opposite to the second redistribution layer of the chip and the second conductive pad is exposed from a surface of the second redistribution layer, wherein an area of the chip is smaller than that of the image sensor chip, and the second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip;
- a molding material layer formed on the image sensor chip, overlying the chip;
- and
- a plurality of metal conductive pillars formed on the first redistribution layer, passing through the molding material layer and being exposed therefrom.
A chip scale package structure, comprising:
- a first chip comprising a first redistribution layer comprising a first conductive wire and a first conductive pad formed on the first conductive wire, wherein the first conductive pad is exposed from a surface of the first redistribution layer;
- a second chip comprising a plurality of through silicon via (TSV) and a second redistribution layer comprising a second conductive wire and a second conductive pad formed on the second conductive wire, wherein the plurality of through silicon via (TSV) extend from the second redistribution layer to a surface opposite to the second redistribution layer of the second chip and the second conductive pad is exposed from a surface of the second redistribution layer, wherein an area of the second chip is smaller than that of the first chip, and the second redistribution layer of the second chip bonds to the first redistribution layer of the first chip;
- a molding material layer formed on the first chip, overlying the second chip;
- and
- a plurality of metal conductive pillars formed on the first redistribution layer, passing through the molding material layer and being exposed therefrom.
Dependencies are inferred from the claim text.