Semiconductor memory structure and method of manufacturing the same

A semiconductor memory structure, comprising:

• a substrate;
• a cell array region formed on the substrate and comprising a plurality of cell strings including source structures and drain structures;
• at least one connection region formed on the substrate and beside the cell array region, and comprising:
• a plurality of rows of first conductive pillars formed over the substrate, wherein each of the first conductive pillars extends along a first direction, and each row of the first conductive pillars are arranged in a second direction;
• a plurality of rows of second conductive pillars formed over the substrate, wherein each of the second conductive pillars extends along the first direction, and each row of the second conductive pillars are arranged in the second direction, and wherein the rows of the first conductive pillars and the rows of the second conductive pillars are alternately arranged along a third direction;
• and
• a ferroelectric layer disposed between the rows of first conductive pillars and the rows of second conductive pillars:
• a first interconnect structure formed on the cell array region and connecting to the source structures and the drain structures of the cell strings;
• and
• a second interconnect structure formed on the connection region, coupling to the first conductive pillars and the second conductive pillars, and comprising a plurality of vias formed on the first conductive pillars and the second conductive pillars to allow one of the first conductive pillars and one of the second conductive pillars connect to one via,
• wherein the vias on the first conductive pillars and the second conductive pillars are arranged in a XY staggered pattern.

A method of manufacturing a semiconductor memory structure, the method comprising:

• forming a stack of alternating insulating layers and sacrificial layers over a substrate;
• forming trenches in the stack;
• replacing the sacrificial layers with conductive layers;
• filling each trench with a multi-layered structure including a ferroelectric layer and a semiconductor layer;
• removing portions of the multi-layered structure to form a plurality of cell strings in a cell array region and to form a plurality of conductive pillars in connection regions;
• and
• forming a first interconnect structure to connect to the cell strings in the cell array region and forming a second interconnect structure to connect to the conductive pillars in the connection regions,
• wherein forming the second interconnect structure comprises forming vias in a XY staggered pattern on the conductive pillars.