Semiconductor memory device and method of manufacturing the semiconductor memory device
AssigneeSK hynix Inc.
InventorNam Jae Lee
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Abstract
Provided herein may be a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a stacked body including alternately stacked interlayer insulating layers and conductive patterns, and channel structures penetrating the stacked body. Each of the channel structures may include a channel layer vertically extending up to the height of the upper portion of at least one upper conductive pattern disposed uppermost, among the conductive patterns, a memory layer surrounding the channel layer and extending from the lower interlayer insulating layer to the height of the middle portion of the upper conductive pattern, and a doped semiconductor pattern disposed above the channel layer and the memory layer.
Claims14
A semiconductor memory device, comprising:
- a stacked body including alternately stacked interlayer insulating layers and conductive patterns;
- and
- channel structures penetrating the stacked body,
- wherein each of the channel structures includes
- a channel layer vertically extending up to a height of an upper portion of at least one upper conductive pattern disposed uppermost, among the conductive patterns;
- a memory layer surrounding the channel layer and extending from a lower interlayer insulating layer to a height of a middle portion of the upper conductive pattern;
- and
- a doped semiconductor pattern disposed above the channel layer and the memory layer.
A semiconductor memory device, comprising:
- a stacked body including alternately stacked interlayer insulating layers and conductive patterns;
- and
- channel structures penetrating the stacked body,
- wherein each of the channel structures includes:
- a channel layer extending up to a height of a portion of at least one upper conductive pattern disposed uppermost, among the conductive patterns;
- a memory layer surrounding the channel layer and extending up to a height of the upper conductive pattern and lower than an upper surface of the channel layer;
- and
- a doped semiconductor pattern disposed above the channel layer and the memory layer,
- the channel layer including a protrusion, which protrudes with respect to an upper surface of the memory layer and extends into the doped semiconductor pattern.
Dependencies are inferred from the claim text.