Memory device having vertical structure including a first wafer and a second wafer stacked on the first wafer

A memory device comprising:

• a first wafer, and a second wafer stacked on and bonded to the first wafer,
• wherein the first wafer comprises:
• a cell structure including a memory cell array;
• and
• a first logic structure disposed under the cell structure, and including a column control circuit,
• wherein the second wafer comprises a second logic structure including a row control circuit,
• wherein the memory cell array comprises a stack structure that is disposed on a source plate in a cell region and a slimming region, and bit lines disposed over the stack structure,
• wherein the cell structure includes a source electrode that is coupled to the source plate through a contact structure passing through the stack structure, and
• wherein the source electrode is disposed in the cell region of a wiring layer between the bit lines and the second wafer.