Manufacturing method for memory structure

A manufacturing method for a memory structure, comprising:

• forming a plurality of gate stack structures on a substrate;
• forming a spacer layer on a sidewall of the plurality of gate stack structures, wherein the spacer layer is connected between the two adjacent gate stack structures;
• forming a protective material layer covering the spacer layer and the plurality of gate stack structures;
• forming a mask material layer on the protective material layer, wherein the mask material layer has a void between the two adjacent gate stack structures, and a first distance is larger than the sum of a second distance and a third distance, wherein the first distance is between the top of the protective material layer directly located above the plurality of gate stack structures and the top of the mask material layer directly located above the plurality of gate stack structures, the second distance is between the top of the void and the top of the mask material layer directly located above the void, and the third distance is between the bottom of the void and the bottom of the mask material layer located directly below the void;
• performing an etching process on the mask material layer to form a plurality of first mask layers separated from each other, wherein the plurality of first mask layers cover the protective material layer on the plurality of gate stack structures, and expose a portion of the protective material layer located between the bottoms of the two adjacent gate stack structures;
• and
• removing a part of the protective material layer exposed by the plurality of first mask layers to form a plurality of protective layers separated from each other.