Metal insulator semiconductor (MIS) contact in three dimensional (3D) vertical memory

A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising:

• forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through a vertical stack of a first dielectric material, a semiconductor material having a channel region, and a second dielectric material, the vertical opening extending predominantly in the second horizontal direction to form elongated vertical, pillar columns with sidewalls in the vertical stack;
• conformally depositing a first conductive material on a gate dielectric material in first alternating ones of the plurality of first vertical openings;
• removing portions of the first conductive material in first alternating ones of the plurality of first vertical openings to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns;
• conformally depositing a first conductor material on an insulator material in second alternating ones of the plurality of first vertical openings;
• removing portions of the first conductor material and the insulator material in second alternating ones of the plurality of first vertical openings to form a plurality of separate, vertical metal insulator semiconductor (MIS) interfaces to channel regions;
• forming a second vertical opening extending predominantly in the first horizontal direction through the vertical stack to expose vertical sidewalls in the vertical stack;
• selectively etching the second dielectric material to form a first horizontal opening;
• gas phase doping a dopant in a top surface of the low doped semiconductor material to form the first source/drain region;
• and
• depositing a second conductor material above the first source/drain region to form a digit line in the first horizontal opening.

A memory device, comprising:

• an array of vertically stacked memory cells, the array of vertically stacked memory cells, comprising:
• horizontally oriented access devices having a first source/drain region and a second source drain region separated by a horizontal channel region, and gates opposing the horizontal channel region and separated therefrom by a gate dielectric;
• vertically oriented access lines coupled to the gates and separated from the horizontal channel region by the gate dielectric;
• horizontally oriented storage nodes electrically coupled to the second source/drain regions of the horizontally oriented access devices;
• horizontally oriented digit lines electrically coupled to the first source/drain regions of the horizontally oriented access devices;
• horizontally formed metal insulator semiconductor (MIS) interfaces between the first source/drain regions and the digit lines;
• and
• a vertical body contact formed in direct, electrical contact with a body region of one or more of the horizontally oriented access devices and separated from the first source/drain region and the horizontally oriented digit lines by a dielectric.