Structures and methods for memory cells
AssigneeIntel Corporation
InventorsSean T. Ma, Aaron D. Lilak, Abhishek A. Sharma, Van H. Le, Seung Hoon Sung, Gilbert W. Dewey, Benjamin Chu-Kung, Jack T. Kavalieros, Tahir Ghani
Life of this patent
Estimating the term…
Abstract
Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.
Claims25
A memory device, comprising:
- a support having a surface;
- and
- a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells in the three-dimensional array include a transistor and a capacitor, a channel of the transistor in an individual memory cell is oriented parallel to the surface, a first end of the channel of the transistor in an individual memory cell is in electrical contact with the capacitor of the individual memory cell, a second end of the channel is in electrical contact with a bit line, and the bit line is oriented perpendicular to the surface.
An integrated circuit (IC) die, comprising:
- a memory device including:
- a support having a surface, and
- a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, individual memory cells in the three-dimensional array are arranged into a two-dimensional array of columns oriented perpendicular to the surface, individual capacitors in individual memory cells include a first plate, a second plate, and a capacitor dielectric between the first plate and the second plate, and the capacitor dielectric of different ones of the capacitors in an individual column of memory cells is provided by a continuous portion of capacitor dielectric.
A computing device, comprising:
- an integrated circuit (IC) package, including:
- a package substrate, and
- a die coupled to a surface of the package substrate, wherein the die includes a memory device, the memory device includes a support having a surface, a three-dimensional array of memory cells on the surface of the support, and a word line, wherein individual memory cells include a transistor and a capacitor, wherein the word line is spaced apart from a channel of the transistor in an individual memory cell by a gate dielectric, and wherein the gate dielectric extends continuously between the word line and the channel of the transistor, between the word line and the capacitor, and between the word line and an insulating material.
Dependencies are inferred from the claim text.