Power converter with an upper arm and a lower arm and at least first and second semiconductor devices connected by a bridging member

A power converter comprising:

• an upper arm and a lower arm connected in series;
• the upper arm including at least one first semiconductor device that includes a plurality of first semiconductor chips, each of the plurality of first semiconductor chips has a first switching element, and a plurality of first main terminals which are connected to the plurality of first semiconductor chips and provide an electric connection function, the first switching elements being connected in parallel and the plurality of first main terminals including at least one first high potential terminal connected to an electrode of the first switching element on a high potential side and at least one first low potential terminal connected to an electrode of the first switching element on a low potential side;
• the lower arm including at least one second semiconductor device that includes a plurality of second semiconductor chips, each of the plurality of second conductor chips has a second switching element, and a plurality of second main terminals which are connected to the plurality of second semiconductor chips and provide an electric connection function, the second switching elements being connected in parallel, and the plurality of second main terminals including at least one second high potential terminal connected to an electrode of the second switching element on the high potential side and at least one second low potential terminal connected to an electrode of the second switching element on the low potential side;
• and
• a bridging member that bridges the at least one first low potential terminal and the at least one second high potential terminal, and provides an upper and lower coupling portion between the upper arm and the lower arm with the at least one first low potential terminal and the at least one second high potential terminal, wherein:
• in the at least one first semiconductor device,
• the plurality of first semiconductor chips are in line symmetry with respect to a first axis perpendicular to a first direction in which at least two of the plurality of first semiconductor chips are aligned, and
• the at least one first high potential terminal and the at least one first low potential terminal are each in line symmetry with respect to the first axis as a symmetry axis;
• and
• in the at least one second semiconductor device,
• the plurality of second semiconductor chips are in line symmetry with respect to a second axis perpendicular to a second direction in which at least two of the plurality of second semiconductor chips are aligned,
• the at least one second high potential terminal and the at least one second low potential terminal are each in line symmetry with respect to the second axis as the symmetry axis, and
• an arrangement of the at least one second low potential terminal relative to the at least one second high potential terminal is different from an arrangement of the at least one first low potential terminal relative to the at least one first high potential terminal.