Semiconductor memory device including a memory chip and a circuit chip bonded to the memory chip

A semiconductor memory device comprising:

• a memory chip, wherein the memory chip includes:
• a first region including a plurality of first memory cells and second memory cells;
• a second region different from the first region;
• a plurality of first word lines stacked apart from each other in a first direction in the first region and the second region;
• a first pillar including a first semiconductor layer extending through the plurality of first word lines, and a first insulator layer provided between the first semiconductor layer and the plurality of first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines;
• a first bonding pad in the second region;
• and
• a first transistor between the plurality of first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region;
• and
• a circuit chip bonded to the memory chip, wherein the circuit chip includes:
• a substrate;
• a second bonding pad facing the first bonding pad of the memory chip;
• and
• a control circuit provided on the substrate, and electrically connected to the first transistor via the first bonding pad and the second bonding pad.