High voltage semiconductor devices having improved electric field suppression

A semiconductor device having a corresponding operating maximum voltage, the semiconductor device comprising:

• a metal-oxide-semiconductor field-effect transistor (MOSFET) element;
• one or more isolation layers formed over a surface of the MOSFET element;
• a patterned electric field (E-field) suppression layer formed over the one or more isolation layers, wherein the E-field suppression layer comprises a film bonded to an isolation layer of the one or more isolation layers over a termination region of the MOSFET, wherein the E-field suppression layer is configured to suppress an electrical field strength produced by the MOSFET element such that the electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at the maximum voltage;
• and
• a metallization layer formed at least partially above the E-field suppression layer to form a power overlay (POL) structure configured to enlarge an underlying bonding area, wherein the POL structure comprises the E-field suppression layer with a thickness in the range of 50 μm-200 μm;
• wherein the one or more isolation layers comprises a passivation layer formed below the E-field suppression layer and a dielectric layer formed, with a different material, over the passivation layer and below the E-field suppression layer.

A semiconductor device having a corresponding operating maximum voltage, the semiconductor device, comprising:

• a silicon carbide (SiC) substrate;
• a termination region formed on the SiC substrate;
• metal contact areas formed on the SiC substrate;
• an electric field (E-field) suppression layer formed over the termination region, wherein the E-field suppression layer comprises a film bonded to an isolation layer over the termination region, wherein the E-field suppression layer is patterned with openings over the metal contact areas, and wherein the E-field suppression layer comprises a thickness such that an electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at the maximum voltage;
• the isolation layer comprising a passivation layer formed below the E-field suppression layer and a dielectric layer formed, with a different material, over the passivation layer and below the E-field suppression layer;
• and
• a metallization layer formed at least partially above the E-field suppression layer to form a power overlay (POL) structure configured to enlarge an underlying bonding area, wherein the POL structure comprises the E-field suppression layer with a thickness in the range of 50 μm-200 μm.