Semiconductor package having molded die and semiconductor die and manufacturing method thereof

A semiconductor package, comprising:

• a first semiconductor die, comprising a first metal post exposed at a front surface of the first semiconductor die;
• a second semiconductor die, comprising stacked chips encapsulated in a first encapsulant, the second semiconductor die comprising a contact pad;
• joint micro-bumps disposed on the contact pad of the second semiconductor die;
• a second encapsulant, encapsulating the second semiconductor die and the joint micro-bumps;
• a third encapsulant, encapsulating the first semiconductor die and the second encapsulant;
• a dielectric layer extending on the third encapsulant and the first semiconductor die and comprising openings exposing front surfaces of the first metal post and of the joint micro-bumps;
• and
• a redistribution conductive layer disposed on the dielectric layer, and extending in the openings of the dielectric layer to contact the front surfaces of the first metal post and of the joint micro-bumps.

A manufacturing method of a semiconductor package, comprising:

• providing first semiconductor dies, wherein each first semiconductor die comprises stacked chips, a first encapsulant, and a contact pad, the stacked chips are encapsulated in the first encapsulant, and the contact pad is over the stacked chips;
• forming joint micro-bumps on the contact pads of the first semiconductor dies;
• molding the first semiconductor dies and the joint micro-bumps in a second encapsulant to form a first reconstructed wafer;
• reducing a thickness of the first reconstructed wafer;
• cutting through the first reconstructed wafer to obtain first molded dies, wherein the first molded dies comprise at least one first semiconductor die of the first semiconductor dies, and variations in initial thicknesses of the first semiconductor dies are greater than variations in thicknesses of the first molded dies;
• encapsulating the second encapsulant of the first molded dies and second semiconductor dies in a third encapsulant to form a second reconstructed wafer, wherein each second semiconductor die comprises a metal post exposed at a front surface of the second semiconductor die;
• reducing a thickness of the second reconstructed wafer;
• and
• forming a redistribution structure on the second reconstructed wafer, the redistribution structure being electrically connected to the first molded dies and the second semiconductor dies, wherein the redistribution structure comprises a dielectric layer and a redistribution conductive layer, the dielectric layer extends on the third encapsulant and the second semiconductor dies, the dielectric layer comprises openings exposing front surfaces of the metal post and of the joint micro-bumps, the redistribution conductive layer is disposed on the dielectric layer and extends in the openings of the dielectric layer to contact the front surfaces of the metal post and of the joint micro-bumps.