Electronic chip with under-side power block

A method, comprising:

• forming a chip package having a first major side and a second major side, comprising:
• forming an insulator;
• forming interconnect circuitry embedded in the insulator, comprising:
• a plurality of conductive layers;
• a plurality of insulating layers, individual ones of the plurality of insulating layers positioned between individual ones of the plurality of conductive layers;
• a conductive through hole, electrically connecting a first pair of the plurality of conductive layers through a first one of the plurality of insulating layers with a through hole conductive material defining a first width and having a side wall perpendicular to the first and second major sides;
• and
• a via, electrically connecting a second pair of the plurality of conductive layers through a second one of the plurality of insulating layers with a via conductive material defining a second width less than the first width, the via electrically coupling the conductive through hole with another one of the plurality of conductive layers different than the first pair of the plurality of conductive layers;
• securing a power block to the second major side and electrically coupling the power block to the interconnect circuitry, comprising:
• a power source configured to provide power to components of the electronic chip;
• and
• a relay circuit coupled to the power source and a ground plane;
• and
• securing electrical connections to the second major side and electrically coupling the electrical connections to the interconnect circuitry.

A system, comprising:

• a circuit board;
• and
• an electronic chip, secured and electrically coupled to the circuit board, comprising:
• a power block, comprising:
• a power source configured to provide power to components of the electronic chip;
• and
• a relay circuit coupled to the power source and a ground plane;
• a chip package having a first major side facing away from the circuit board and a second major side facing the circuit board, the power block secured to the second major side, the chip package comprising:
• electrical connections, disposed on the second major side, secured to the circuit board;
• and
• interconnect circuitry, electrically coupling the power block to ground, comprising:
• a plurality of conductive layers;
• a plurality of insulating layers, individual ones of the plurality of insulating layers positioned between individual ones of the plurality of conductive layers;
• a conductive through hole, electrically connecting a first pair of the plurality of conductive layers through a first one of the plurality of insulating layers with a through hole conductive material defining a first width and having a side wall perpendicular to the first and second major sides;
• and
• a via, electrically connecting a second pair of the plurality of conductive layers through a second one of the plurality of insulating layers with a via conductive material defining a second width less than the first width, the via electrically coupling the conductive through hole with another one of the plurality of conductive layers different than the first pair of the plurality of conductive layers.