Interconnect structure

A method of forming an integrated chip, comprising:

• forming a sacrificial layer to cover a first interconnect within a first inter-level dielectric (ILD) over a substrate;
• selectively forming an etch stop structure over the first ILD without being formed over the sacrificial layer, wherein the etch stop structure covers the first ILD and laterally contacts the sacrificial layer;
• forming a second ILD onto the etch stop structure and the sacrificial layer;
• etching the second ILD to form an opening that exposes the sacrificial layer;
• removing the sacrificial layer after etching the second ILD, wherein removing the sacrificial layer exposes a part of the first interconnect;
• and
• forming a conductive material within the opening and on the part of the first interconnect.

A method of forming an integrated chip, comprising:

• forming an interconnect patterning layer on an upper surface of a first interconnect within a first inter-level dielectric (ILD) layer over a substrate;
• forming an etch stop structure to cover an upper surface of the first ILD layer;
• forming an upper etch stop structure directly over the etch stop structure and the interconnect patterning layer, the upper etch stop structure continuously and laterally extending past one or more outermost sidewalls of the etch stop structure to directly over the interconnect patterning layer;
• forming a second ILD layer onto the upper etch stop structure;
• etching the second ILD layer to form an opening that exposes the interconnect patterning layer and an upper surface of the upper etch stop structure;
• removing a part of the interconnect patterning layer to expose the upper surface of the first interconnect after etching the second ILD layer;
• and
• forming a second interconnect onto the upper surface of the first interconnect and onto the upper surface of the upper etch stop structure.