Vertical bond-wire stacked chip-scale package with application-specific integrated circuit die on stack, and methods of making same

A memory module in a system in package apparatus comprising:

• a matrix including a landing surface;
• a memory-die stack configured in a stair-step relationship and seated in the matrix, the memory-die stack including a first memory die and a subsequent memory die, the first memory die including an active surface and a backside surface and the subsequent memory die including an active surface and a backside surface, wherein the first memory die includes a vertical first bond wire that extends at a non-orthogonal angle from the first memory die active surface and breaches the matrix landing surface, and the subsequent memory die includes a vertical subsequent bond wire that extends from the subsequent memory die active surface and breaches the matrix landing surface;
• a processor first die disposed on the first memory die and at least partially seated in the matrix, the processor first die including an active surface and a backside surface, wherein a processor bump array is disposed on the first memory die active surface, and wherein the processor bump array extends at least partially away from the matrix landing surface;
• a spacer, separate from the matrix, and disposed within the matrix, the spacer disposed on the first memory die, and wherein the spacer is disposed laterally between the processor first die and the first memory die vertical first bond wire.

A computing system including a memory-die stack in a memory module in a system in package apparatus comprising a board, and mounted on the board:

• a matrix including a landing surface;
• a memory-die stack configured in a stair-step relationship and seated in the matrix, the memory-die stack including a first memory die and a subsequent memory die, the first memory die including an active surface and a backside surface and the subsequent memory die including an active surface and a backside surface, wherein the first memory die includes an orthogonal first bond wire that extends from the first memory die active surface and breaches the matrix landing surface, and the subsequent memory die includes an orthogonal subsequent bond wire that extends from the subsequent memory die active surface and breaches the matrix landing surface;
• a processor first die disposed on the first memory die and at least partially seated in the matrix, the processor first die including an active surface and a backside surface, wherein a processor bump array is disposed on the processor first die active surface, and wherein the processor bump array extends at least partially away from the matrix landing surface;
• a spacer, separate from the matrix, and disposed within the matrix, the spacer disposed on the first memory die, and wherein the spacer is disposed laterally between the processor first die and the first memory die orthogonal first bond wire;
• and
• wherein the board includes an outer shell that electrically insulates the memory-die stack and the processor first die.