Stacked transistors with different channel widths
AssigneeTessera, Inc.
InventorsKangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthiharan, John Zhang
Life of this patent
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Abstract
A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.
Claims17
A semiconductor integrated circuit comprising:
- a first stack of nanowires above a substrate;
- a first gate structure over, around, and between the first stack of nanowires;
- a second stack of nanowires above the substrate;
- a second gate structure over, around, and between the second stack of nanowires;
- a first source/drain region contacting a first number of nanowires of the first nanowire stack;
- a second source/drain region contacting a second number of nanowires of the second nanowire stack;
- wherein the first number and second number of contacted nanowires are different;
- a first dielectric region between the first source/drain region and the substrate;
- and
- a second dielectric region between the second source/drain region and the substrate,
- wherein the first and second dielectric regions are different in thickness.
A semiconductor integrated circuit comprising:
- a first stack of nanowires above a substrate;
- a first gate structure over, around, and between the first stack of nanowires;
- a second stack of nanowires above the substrate;
- a second gate structure over, around, and between the second stack of nanowires;
- a first source/drain region contacting a first number of nanowires of the first nanowire stack;
- a second source/drain region contacting a second number of nanowires of the second nanowire stack;
- wherein the first number and second number of contacted nanowires are different and the number of nanowires in the first and second nanowire stacks is the same;
- a first dielectric region between the first source/drain region and the substrate;
- and
- a second dielectric region between the second source/drain region and the substrate, wherein the first and second dielectric regions are different in thickness.
Dependencies are inferred from the claim text.