Method for fabricating a device comprising a PNP bipolar transistor and NPN bipolar transistor for radiofrequency applications

A method for fabricating a microelectronic device that includes a PNP transistor and an NPN transistor, comprising:

• forming an N+ doped isolating well of the PNP transistor in a semiconductor substrate that is P-type doped;
• forming a P+ doped region in the N+ doped isolating well;
• epitaxially growing a first epitaxial semiconductor layer on the P+ doped region, on the N+ doped isolating well, and on the semiconductor substrate;
• implanting and activating dopant at an upper surface of the first epitaxial semiconductor layer to form an N+ doped well of the NPN transistor in the first epitaxial semiconductor layer, wherein at least part of said N+ doped well extends from the upper surface and through the first epitaxial semiconductor layer to contact the semiconductor substrate;
• epitaxially growing a second epitaxial semiconductor layer on an upper surface of the N+ doped well and on the upper surface of the first epitaxial semiconductor layer;
• implanting and activating dopant at an upper surface of the second epitaxial semiconductor layer to form a P doped region configured to form a collector of the PNP transistor in the second epitaxial semiconductor layer, wherein at least part of said P doped region extends from the upper surface and through the second epitaxial semiconductor layer to contact the P+ doped region;
• forming a base of the PNP transistor in contact with the P doped region configured to form the collector of the PNP transistor;
• forming an N doped region configured to form a collector of the NPN transistor in the second epitaxial semiconductor layer, wherein at least a portion of the N doped region extends to contact the N+ doped well;
• and
• forming a base of the NPN transistor in contact with the N doped region configured to form the collector of the NPN transistor.

A method for fabricating a microelectronic device that includes a PNP transistor and an NPN transistor, comprising:

• forming an N+ doped isolating well of the PNP transistor in a semiconductor substrate that is P-type doped;
• forming a P+ doped region in the N+ doped isolating well;
• epitaxially growing a first epitaxial semiconductor layer on the semiconductor substrate;
• after epitaxially growing the first epitaxial semiconductor layer, implanting dopant in the first epitaxial semiconductor layer to form an N+ doped well of the NPN transistor extending into the first epitaxial semiconductor layer;
• then epitaxially growing a second epitaxial semiconductor layer on the first epitaxial semiconductor layer;
• forming a P doped region in the second epitaxial semiconductor layer, wherein said P doped region is in electrical contact with the P+ doped region in the N+ doped isolating well;
• forming a base of the PNP transistor in contact with the P doped region which forms a collector of the PNP transistor;
• forming an N doped region in the second epitaxial semiconductor layer, wherein the N doped region is in electrical contact with the N+ doped well;
• and
• forming a base of the NPN transistor in contact with the N doped region which forms a collector of the NPN transistor.