Packaging method, panel assembly, wafer package and chip package

A method for packaging a semiconductor device, comprising:

• providing at least one wafer having a plurality of unsingulated semiconductor dies, wherein the at least one wafer comprises a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface, the first surface being an active surface;
• forming a connection portion on the side surface of the at least one wafer surrounding the wafer, forming a panel assembly with the wafer and the connection portion, the connection portion comprising a third surface on the same side of the first surface of the wafer and a fourth surface on the same side as the second surface of the wafer, the third surface and the first surface forming a to-be-processed surface of the panel assembly;
• and
• forming a first dielectric layer on the first surface of the wafer, wherein the first dielectric layer covers the first surface of the wafer entirely,
• wherein forming the connection portion comprises forming a conductive member, the conductive member being exposed in the third surface of the connection portion, located in a peripheral area of the panel assembly and spaced apart from the wafer.