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US 11,538,549 B2Granted
Test circuit and semiconductor memory system including the test circuit
AssigneeSK hynix Inc.
InventorsJong Seok Jung, Sung Won Choi
Life of this patent
Estimating the term…
Abstract
A test circuit includes a control circuit and a counting circuit. The control circuit is configured to control a charging operation and a discharging operation on a test node. The counting circuit is configured to generate counting information by performing a counting operation during a unit measurement interval.
Claims23
A test circuit comprising:
- a control circuit configured to control a charging operation and a discharging operation on a test node of a test target circuit;
- and
- a counting circuit configured to generate counting information corresponding to a defect of the test node by performing a counting operation which counts a counting clock signal during a unit measurement interval from a point of time that the charging operation on the test node is completed to a point of time that the discharging operation on the test node is completed,
- wherein the counting circuit performs the counting operation based on at least one control signal of a charging control signal and a discharging control signal.
1 more element
A test circuit comprising:
- a control circuit configured to control a charging operation and a discharging operation on a test node of a test target circuit;
- a setting circuit configured to set a total measurement interval based on interval extension information and a unit measurement interval from a point of time that the charging operation on the test node is completed to a point of time that the discharging operation on the test node is completed;
- and
- a counting circuit configured to generate counting information corresponding to a defect of the test node by counting a counting clock signal during the total measurement interval corresponding to an output signal of the setting circuit.
1 more element
A semiconductor memory system comprising:
- a memory circuit having a plurality of memory cells coupled to a word line;
- and
- a test circuit configured to perform a charging operation and a discharging operation on a test node coupled to the word line, and generate counting information corresponding to a defect of the test node by performing a counting operation during a unit measurement interval from a point of time that the charging operation on the test node is completed to a point of time that the discharging operation on the test node is completed,
- wherein the test circuit performs the counting operation based on at least one control signal of a charging control signal and a discharging control signal.
1 more element
Dependencies are inferred from the claim text.