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US 11,538,548 B2Granted
Repair analysis circuit and memory including the same
AssigneeSK hynix Inc.
InventorHosung Cho
Life of this patent
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Abstract
A memory may include a first repair analysis circuit suitable for storing an input fail address when the input fail address is different from a fail address which is already stored in the first repair analysis circuit, and outputting the input fail address as a first transfer fail address when a storage capacity of the first repair analysis circuit is full; and a second repair analysis circuit suitable for storing the first transfer fail address when the first transfer fail address is different from a fail address which is already stored in the second repair analysis circuit.
Claims5
A repair analysis circuit comprising:
- first to Xth repair address registers each suitable for storing a fail address therein where X is an integer equal to or greater than 2;
- and
- a redundancy check circuit suitable for receiving an input address set including one or more addresses and input fail information indicating whether the input address set is a fail, and checking whether a fail address within the input address set is same as one of fail addresses already stored in the first to Xth repair address registers,
- wherein when it is determined that the fail address within the input address set is different from one of the fail addresses already stored in the first to Xth repair address registers, the corresponding fail address is stored in an empty repair address register among the first to Xth repair address registers.
1 more element
Dependencies are inferred from the claim text.