Data compression for global column repair
AssigneeMicron Technology, Inc.
InventorJason M. Johnson
Life of this patent
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Abstract
Methods, systems, and devices for data compression for global column repair are described. In some cases, a testing device may perform a first internal read operation to identify errors associated with on one or more column planes. A value (e.g., a bit) indicating whether an error occurred when testing each column plane may be stored. The testing device may perform a second internal read operation on the same column planes, or on column planes of a different bank of memory cells. The values (e.g., bits) indicating whether errors occurred during the first internal read operation and the values indicating whether errors occurred during the second internal read operation may be combined and stored in a register. The stored values may be read out (e.g., as a burst) to repair the defective column planes.
Claims20
A method, comprising:
- generating, using a first read operation, first data to identify one or more errors associated with memory cells of a first plurality of column planes of a memory device, the first data comprising a first plurality of indicators about whether each column plane of the first plurality of column planes includes the one or more errors;
- generating, using a second read operation, second data to identify one or more errors associated with memory cells of a second plurality of column planes of the memory device, the second data comprising a second plurality of indicators about whether each column plane of the second plurality of column planes includes the one or more errors;
- combining the first data and the second data, by oring bits of the first data with bits of the second data, into a third data that comprises a third plurality of indicators about whether the first plurality of column planes and the second plurality of column planes include one or more errors;
- and
- communicating, by the memory device, a message that includes the third data formed by combining the first data and the second data.
An apparatus, comprising:
- a memory array comprising a first plurality of column planes and a second plurality of column planes;
- and
- a tester coupled with the memory array and the tester configured to cause the apparatus to:
- generate first data to identify one or more errors associated with memory cells of the first plurality of column planes;
- generate second data to identify one or more errors associated with memory cells of the second plurality of column planes of the memory array;
- combine the first data and the second data, by oring bits of the first data with bits of the second data, into third data that comprises a third plurality of indicators about whether the first plurality of column planes and the second plurality of column planes include one or more errors;
- and
- communicate a message that includes the third data formed by combining the first data and the second data.
An apparatus, comprising:
- a memory array comprising a plurality of memory cells, the plurality of memory cells comprising a first plurality of column planes and a second plurality of column planes;
- a data generation component configured to generate first data to identify one or more errors associated with the first plurality of column planes and second data to identify one or more errors associated with the second plurality of column planes;
- a data combining component configured to combine the first data with the second data, by wino bits of the first data with bits of the second data, into third data that comprises a plurality of indicators about whether the first plurality of column planes and the second plurality of column planes include one or more errors;
- and
- a transmission component configured to transmit a message that includes the third data formed by combining the first data and the second data.
Dependencies are inferred from the claim text.