Semiconductor memory device having insulating layers disposed between a plurality of memory string structures

A semiconductor memory device comprising:

• a plurality of first conductive layers arranged in a first direction and extending in a second direction intersecting with the first direction;
• a plurality of second conductive layers spaced from the plurality of first conductive layers in a third direction intersecting with the first direction and the second direction, the plurality of second conductive layers being arranged in the first direction and extending in the second direction;
• a first semiconductor layer disposed between the plurality of first conductive layers and the plurality of second conductive layers, the first semiconductor layer extending in the first direction and opposing the plurality of first conductive layers and the plurality of second conductive layers;
• a charge storage layer that includes a first part and a second part, the first part being disposed between the plurality of first conductive layers and the first semiconductor layer, and the second part being disposed between the plurality of second conductive layers and the first semiconductor layer;
• an insulating layer disposed between the plurality of first conductive layers and the plurality of second conductive layers, the insulating layer extending in the first direction and arranged with the first semiconductor layer in the second direction;
• a first wiring electrically connected to the first semiconductor layer, wherein
• the semiconductor memory device is configured to execute:
• a first erase operation that supplies a first voltage to at least a part of the plurality of first conductive layers, supplies a second voltage larger than the first voltage to at least a part of the plurality of second conductive layers, and supplies an erase voltage larger than the first voltage to the first wiring;
• a second erase operation that supplies the first voltage to at least a part of the plurality of second conductive layers, supplies the second voltage to at least a part of the plurality of first conductive layers, and supplies the erase voltage to the first wiring;
• and
• a first program operation that supplies a first program voltage larger than the first voltage to one of the plurality of first conductive layers and supplies a write pass voltage to another of the plurality of first conductive layers, the write pass voltage being larger than the first voltage and smaller than the first program voltage, wherein the semiconductor memory device executes the first program operation to at least a part of the plurality of first conductive layers after the execution of the first erase operation and before the execution of the second erase operation.