Apparatus for rapid data destruction

An apparatus, comprising:

• a string of series-connected memory cells comprising a first memory cell and a plurality of second memory cells;
• a plurality of access lines, each access line of the plurality of access lines connected to a control gate of a respective memory cell of the string of series-connected memory cells;
• and
• a controller for access of the string of series-connected memory cells, wherein the controller is configured to cause the apparatus to:
• apply a first programming pulse to the access line of the plurality of access lines connected to a control gate of the first memory cell, wherein the first programming pulse has a voltage level sufficient to increase a threshold voltage of the first memory cell to a voltage level sufficient to cause the first memory cell to remain deactivated during a read operation on the string of series-connected memory cells;
• and
• concurrently apply a second programming pulse to each access line of the plurality of access lines connected to a control gate of a second memory cell of the plurality of second memory cells, wherein the second programming pulse has a voltage level sufficient to increase threshold voltages of at least a portion of the plurality of second memory cells.

An apparatus, comprising:

• a first controller;
• and
• a memory in communication with the first controller, wherein the memory comprises:
• a string of series-connected memory cells connected between a common source and a data line and comprising a plurality of principal memory cells and a plurality of dummy memory cells;
• a plurality of dummy access lines, each dummy access line of the plurality of dummy access lines connected to a control gate of a respective dummy memory cell of the plurality of dummy memory cells;
• a plurality of principal access lines, each principal access line of the plurality of principal access lines connected to a control gate of a respective principal memory cell of the plurality of principal memory cells;
• and
• a second controller for access of the string of series-connected memory cells, wherein the second controller is configured to cause the memory to:
• connect a particular dummy memory cell of the plurality of dummy memory cells to the common source and isolate the particular dummy memory cell from the data line;
• increase a threshold voltage of the particular dummy memory cell of the plurality of dummy memory cells to a voltage level higher than a predetermined pass voltage to be received by a control gate of the particular dummy memory cell during a read operation on the string of series-connected memory cells;
• isolate each principal memory cell of the plurality of principal memory cells from the common source and connect each principal memory cell of the plurality of memory cells to the data line;
• and
• concurrently change a respective data state of a subset of principal memory cells of the plurality of principal memory cells, wherein the subset of principal memory cells comprises more than one principal memory cell of the plurality of principal memory cells.