Non-volatile memory device which utilizes a pulse applied to a bit line and/or a common source line between read operations to reduce noise

A non-volatile memory device, comprising:

• a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line;
• a control logic circuit configured to adjust a voltage applied to the plurality of word lines;
• and
• a channel initialization circuit configured to adjust a voltage applied to the plurality of bit lines and the common source line,
• wherein the control logic circuit applies a pre-charge voltage to the word lines, on which a read operation is executed, among the plurality of word lines from a first time to a second time, applies a read voltage to the word lines on which the read operation is executed from the second time to a third time, applies the read voltage to the word lines, on which no read operation is executed, among the plurality of word lines from the first time to the third time, and executes a recovery operation on the plurality of word lines from the third time to a fourth time, and
• the channel initialization circuit applies an initialization pulse to at least one of the plurality of bit lines and the common source line during at least a period of time between the third time and the fourth time.

A non-volatile memory device, comprising:

• a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of string selection lines, a plurality of ground selection lines, a plurality of bit lines and a common source line;
• a row decoder connected to the plurality of word lines, the plurality of string selection lines and the plurality of ground selection lines;
• a common source line driver connected to the common source line;
• a voltage generator configured to apply a word line voltage to the row decoder;
• a page buffer unit connected to the plurality of hit lines;
• and
• a control logic circuit configured to transfer a voltage control signal for adjusting the word line voltage to the voltage generator, transfer a row address signal including word line information, which identifies the word line to which the word line voltage is applied, to the row decoder, transfer a common source line voltage control signal, which is used to control a common source line voltage applied to the common source line, to the common source line driver, transfer a read voltage to be applied to at least two of the plurality of word lines, and transfer a column address signal including bit line information, which identifies the bit line to which a bit line voltage is to be applied, to the page buffer unit,
• wherein the control logic circuit includes a channel initialization circuit,
• the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and
• the channel initialization circuit applies the initialization pulse between a plurality of read sections at which the read voltage is applied to the at least two word lines,
• wherein the initialization pulse is applied at a time point when application of the read voltage ends.